There is a related technique of, using a plurality of DA converting circuits of low resolution such as eight bits provided in a microcomputer, realizing DA conversion of higher resolution.
Japanese Patent No. 2000-278134 discloses a technique for performing high-resolution DA conversion. According to this technique, a digital signal is divided into upper bits and lower bits, the upper bits and lower bits are each converted to analog signals by low-resolution DA converting circuits, and the analog signals are superimposed with one another as resultant signals of the DA conversion. In particular, the analog signals are superimposed with one another so that the upper bits and the lower bits are partly overlapped, thereby suppressing decrease in the analog signals at the time of carry of digit between the upper and lower bits.
Japanese Patent No. 2008-153928 discloses a system having a first DA converter dividing N bits of digital data into two channels: a first channel of (Na+Nc) bits from the most significant bits (“MSB”) of the digital data and a second channel of (Nc+Nb) bits from the least significant bits (“LSB”) of the digital data, where the first and second channels are coupled to one another, a second DA converter coupled to the second channel, an amplifier amplifying an output of the first DA converter, an adder adding an output of the amplifier and an output of the second DA converter, a subtractor subtracting an output of the second DA converter from an output of the amplifier, and DA conversion corrector that changes a full-scale output value of the second DA converter in accordance with an output of the subtractor, and a technique of realizing high-speed operation, high-resolution, and high-precision multi-bit DA conversion by combining the high-speed and low-cost DA converters of smaller bits.
Japanese Patent No. Sho 58 (1983)-97918 discloses a method of internally and automatically generating correction data for correcting a result of conversion of a DA converter of low resolution by DA converting the upper “i” bits of “n” bits of digital data by a first DA converter, storing error data in an output of the input data of the DA conversion, DA converting the error data in correspondence with the input data of the DA conversion by a second DA converter, further DA converting the lower “j” (which is equal to n−i) bits of the “n” bits of digital data by a third DA converter, combining outputs of the DA converters, comparing the combined data with the error data, and correcting a result of the DA conversion using a comparison result.
Japanese Patent No. Sho 58 (1983)-181323 discloses a system having a converter for converting upper bits of a digital input signal to an analog signal, a converter for converting lower bits of the digital input signal to an analog signal, a circuit alternately generating two arbitrary digital values and detecting the difference between two analog values of the two digital values, a circuit of calculating correction data from the detected difference, and a storage circuit storing the calculated correction data in association with the input digital signal, and a technique of realizing high-linearity DA conversion by correcting an error in an input digital signal to be converted on the basis of the stored correction data.